This invention relates generally to First-In, First-Out (FIFO) circuits, particularly synchronous FIFOs, and to methods of using such synchronous FIFOs.
FIFOs are well-known circuits with many applications. In general, a FIFO includes a storage array made up of multiple rows. Write circuits write input data to a row and use one or more write pointers to determine the next row to be written. Read circuits read data from a row so that it can be provided as an output. Read circuits use one or more read pointers to determine the next row to read so that data is output in the order in which it was input (i.e. following the principle of “first-in, first-out”).
In synchronous FIFOs, both read and write circuits operate based on a common clock. In some cases, while both read and write circuits operate based on a common clock, they may use different multiples of the common clock signal. For example, a clock signal may be used directly as a read clock (read clock frequency=RCLK), while the write clock has a frequency (“WCLK”) that is some multiple of RCLK (e.g. 2*RCLK, 3*RCLK, 4*RCLK . . . etc.).
FIG. 1 shows an example of a synchronous FIFO according to the prior art. A dual port array forms the FIFO storage array in which data is stored in rows. Any suitable device may be used to form individual cells in such an array, for example SRAM, DRAM, flip-flop circuits, or other suitable circuits may be used. Data is received into an input register that is controlled by write control circuits. The write control circuits control transfer of the data from the input register to a row of the FIFO storage array. The write control circuits receive a write clock signal, with a frequency WCLK that determines the timing of data transfer from the input register to the FIFO storage array. A write pointer indicates the next row to be written in the FIFO array.
An output register is used to hold data that is read from a row in the FIFO storage array. The output register is controlled by read control circuits which receive a read clock signal with clock frequency RCLK. Because the example of FIG. 1 is a synchronous FIFO, the read clock is the same as the write clock, or is obtained by dividing the write clock, i.e. RCLK is equal to WCLK, or is a fraction of WCLK (e.g. WCLK/2, WCLK/3 . . . etc.). A read pointer indicates the next row to be read so that the data is read out in the same order in which it was written.
There are many applications for FIFOs in integrated circuits. For example, where data is transferred from one clock domain to another clock domain, a FIFO provides a convenient way to deal with timing issues that may occur because of differences in clock speeds. Synchronous FIFOs may be used where data is transferred between synchronous clock domains where one of the clock domains uses a clock signal that is a divided clock signal. Synchronous FIFOs may also be used in situations where clock speeds are the same at input and output sides, i.e. RCLK=WCLK. One application for synchronous FIFOs is in memory controllers, for example memory controllers used with NAND flash memory, and similar controllers. Such controllers may be formed as Application Specific Integrated Circuits (ASICs) that are customized for a particular application, or set of applications.
Several problems may occur in prior art synchronous FIFOs. For example, when using a high write clock speeds, and when dealing with variable-length data, prior art synchronous FIFOs are found to be inefficient. Thus, there is a need for a synchronous FIFO that can more efficiently deal with various conditions.